The Seoul National University College of Engineering announced that a research team led by Professor Jae Hyuk Choi from the Department of Electrical and Computer Engineering has won the prestigious “ISSCC 2025 Takuo Sugano Award” at the International Solid-State Circuits Conference (ISSCC) 2026, widely regarded as the “Olympics of semiconductor circuit design.”
The award ceremony took place on February 16 in San Francisco. Among 165 papers presented from the Asia-Pacific region, only one was selected for this highest honor, recognizing both technical excellence and academic and industrial impact.
ISSCC: The Global Stage for Semiconductor Innovation
Organized by the Institute of Electrical and Electronics Engineers (IEEE), ISSCC has been the world’s premier conference on solid-state circuits since 1954. Cutting-edge semiconductor technologies from leading global companies and top universities are first unveiled at this annual event, making it a benchmark for industry leadership.
The Takuo Sugano Award is granted to a single paper from the Asia-Pacific region that demonstrates exceptional technical achievement and broad influence. This marks the first time in 20 years that an SNU research team has received this distinction, following its previous win at ISSCC 2005.
Tackling the Core Bottleneck of AI Systems: HBM Power and Heat
The award-winning paper, titled:
“An 850μW 2-to-5GHz Jitter-Filtering and Instant-Toggling Injection-Locked Quadrature-Clock Generator for Low-Power Clock Distribution in HBM Interfaces,”
introduces a breakthrough circuit architecture addressing one of the most critical challenges in modern AI systems—power consumption and heat generation in High Bandwidth Memory (HBM) interfaces.
HBM plays a central role in AI accelerators by enabling ultra-high-speed data transfer between GPUs and memory. To support this bandwidth, more than 2,000 I/O channels must operate simultaneously, requiring multi-phase GHz-range clock signals. Conventional parallel clock distribution architectures consume substantial power, becoming a major source of thermal stress in HBM systems.
A Paradigm Shift in Clock Distribution
Instead of distributing high-frequency multi-phase signals in parallel, Professor Choi’s team proposed a fundamentally new architecture:
A single low-frequency signal carries phase information sequentially (serialized transmission).
The required multi-phase signals are reconstructed locally at the I/O interface just before use.
By shifting complexity from global parallel distribution to localized reconstruction, the team achieved more than a 90% reduction in power consumption compared to conventional approaches—down to just 850μW.
This dramatic improvement directly mitigates heat generation and power density challenges in next-generation AI chips, offering a scalable solution for future high-performance computing platforms.
Reinforcing Korea’s Global Semiconductor Leadership
The significance of this achievement extends beyond academic recognition. As AI workloads intensify and memory bandwidth demands continue to grow, energy-efficient clocking and signal distribution architectures will become increasingly decisive in system competitiveness.
Rather than relying solely on process scaling, the SNU team demonstrated that architectural and circuit-level innovation can unlock transformative efficiency gains. The proposed solution is expected to influence future GPU, AI accelerator, and high-performance server memory interface designs.
First author Jeongbeom Seo, a Ph.D. candidate, stated, “We are honored to contribute meaningfully to the advancement of HBM technology, which is central to Korea’s semiconductor industry. We will continue our research with a strong sense of responsibility amid intense global competition.”
This milestone not only reaffirms Korea’s world-class expertise in semiconductor circuit design but also underscores a broader industry shift: in the AI era, power-efficient architecture is emerging as the decisive frontier of innovation.
